1. Field of the Invention
This invention relates to operational amplifiers (op amps) and more particularly to double-folded cascode op amps.
2. Description of the Related Art
Folded-cascode operational amplifiers have an improved common mode rejection ratio (CMRR) and common mode voltage range (CMVR) compared to more conventional operational amplifiers. A folded-cascode design is described in U.S. Pat. No. 4,687,984 by the present inventor, "JFET Active Load Input Stage". The described circuit is also less likely to go into saturation or cut-off states during high slew rates.
A basic design for the input and gain stages of a folded-cascode operational amplifier is shown in FIG. 1. A pair of differentially connected transistors Q1 and Q2, which can be either bipolar or junction field effect transistors (JFETs), have their current circuits connected together on one side to divide the output of a current source Is. As used herein, a transistor's "current circuit" refers to the collector-emitter circuit of a bipolar transistor, or the source-drain circuit of an FET; a transistor's "control circuit" refers to the base of a bipolar device, or the gate of an FET.
Input terminals T1 and T2, connected respectively to the control circuits for Q1 and Q2, receive a differential input signal. Q1 and Q2 divide the current from Is in mutual opposition, with the amount of current for each transistor varying in accordance with the relative input voltage signals applied to their control circuits from the input terminals T1, T2.
The input current source Is operates from a positive voltage supply bus Vcc, while the collectors of the illustrative pnp input transistors Q1 and Q2 are connected to a relatively negative voltage supply bus (generally ground potential) through respective input resistors R1 and R2.
A gain stage for the amplifier includes first and second active load npn bipolar gain transistors Q3 and Q4, whose emitters are connected to the collectors of input transistors Q1 and Q2, respectively. The bases of Q3 and Q4 are connected together for common biasing. The transistors Q3 and Q4 are supplied with current from current sources I1 and I2, which can be implemented for example by pnp bipolar transistors. A bias circuit for Q3 and Q4 consists of (1) another npn bipolar transistor Q5 that has its emitter connected to the bases of Q3 and Q4, its base connected to the collector of Q3 and its collector connected to Vcc, and (2) a current source I3 that draws current from the common base junction of Q3/Q4 to the ground bus. A gain stage output 2 is taken from the collector of the gain transistor Q4.
The operation of this prior circuit can be explained by assuming that the input voltage at terminal T2 goes up in relation to the voltage at T1. This causes the current through Q1 to increase and the current through Q2 to drop. The increased current through Q1 produces a larger voltage drop across R1, and thus a higher voltage at the bases of Q3 and Q4 (through the emitter follower action of Q3). The higher voltage at the base of Q4 causes the current through that transistor to also go up. In addition, the reduced current through the second input transistor Q2 tends to reduce the voltage across R2. To counteract this effect and keep the voltage across R2 equal to that across R1 (because of the emitter follower action of Q3 and Q4), the current through Q4 increases. The net effect is that, to the first order, there is an increase in current through Q4 equal to twice the absolute magnitude of the current change through either Q1 or Q2. Since current source I2 supplies a constant current level to the gain stage output, any change in the current through Q4 is reflected as an equal absolute change in the output current 2. During this time the base-emitter connection of Q5 across the collector-base terminals of Q3 holds the current level through Q3 constant (to the first order) at the I1 level.
The circuit of FIG. 1 has a limited common mode input range that extends from the low voltage supply line (typically ground) to two base-emitter voltage drops (about 1.4 volts) below Vcc. This was satisfactory for past applications in which positive and negative 15 volt supplies ("rails") were typical. However, amplifiers are presently being designed to work with +5 volt and ground rails, and even +3 volt and ground rails. A primary reason for the steady reduction in power supply levels is the need for lower power dissipation in battery powered electronic devices, such as lap-top computers and cellular telephones. The reduction of over 1 volt from a full rail-to-rail common mode input range is a significant and undesirable loss with these low voltage circuits.
A double-folded cascode operational amplifier has been developed that provides a rail-to-rail input capability. One pair of transistors in the gain stage handles inputs down to the lower rail or below, while another pair of gain stage transistors accommodates input signals up to the upper rail or above. See Goodenough, "Circuit Lets IC OP AMP Handle .+-.0.9-V Rail-To-Rail Signals", Electronic Design, Oct. 1, 1992, page 31; Vyne et al., "A Quad Low Voltage Rail-to-Rail Operational Amplifier", IEEE 1992 Bipolar Circuits and Technology Meeting, pages 242-245. While this circuit has a greater operating range than more conventional folded cascode op amps, the circuitry is quite complex and requires a relatively large number of transistors, which occupy an undesirably large total area and add to the circuit's cost.
It is also important to inhibit input signal voltage offsets, particularly for applications with low voltage supply limits.